Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating-gate transistors in a silicon substrate. A floating-gate transistor is capable of storing electrical charge either on a separate gate electrode, known as a floating gate, or in a dielectric layer underlying a control-gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
In a flash EEPROM device, electrons are transferred to the floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and an underlying substrate. Typically, the electron transfer is carried out by channel hot electron ("CHE") injection or Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode. In one type of device, the control-gate electrode is a polycrystalline silicon-gate electrode overlying the floating-gate electrode and separated therefrom by a dielectric layer. In another type of device, the floating-gate electrode is a doped region in the semiconductor substrate.
Flash memory devices are formed by rows and columns of flash transistors, with each transistor being referred to as a cell. A wordline decoder provides operational voltages to rows of transistors in each sector of the memory device and is typically connected with the gate of each transistor in the sector. A bit line decoder provides operational voltages to columns of transistors and is typically connected to the drains of the transistors in each column. Generally, the sources of the transistors are coupled to a common sourceline and are controlled by a sourceline controller.
A cell is typically programmed by applying a predetermined voltage to the control gate, a second predetermined voltage to the drain, and grounding the source. This causes channel hot electrons to be injected from the drain depletion region into the floating gate. Cells are typically read by applying a predetermined voltage to the control gate, a second predetermined voltage to the bit line, to which the drain is connected, grounding the source, and then sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high, the bit line current will be zero or relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low, the control-gate voltage will enhance the channel and the bit line current will be relatively high.
A cell can be erased several ways in a flash memory device. In one arrangement, a cell is erased by applying a predetermined voltage to the source, grounding the control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source.
A known problem with decoding architecture is that one wordline decoder, and sometimes two wordline decoders, are used to perform the decoding that selects rows of transistors in each sector. These prior art wordline decoding architectures have all of the decoding logic situated at each stage in the wordline decoder. As such, there is no partial decoding in the core area, which contributes to a large wordline decoder size. Because of the large physical size of the wordline decoder, space is wasted on the silicon substrate or extra space is required which increases the size of the memory device.
Known prior art memory wordline decoding architectures use two layers of metal to interconnect the wordline decoder with the cells in the memory device. Due to the very small size of the transistors, the metal lines that are used to connect the transistors with the decoders are extremely difficult to manufacture without experiencing yield loss. This is because the metal lines that connect the various electrical components together are deposited very close together, which leads to shorting and noise problems.
To that end, a need exists for memory devices with an improved method and system of decoding memory wordlines that does not require as much physical space on the substrate and yet does not increase yield loss during manufacturing.